This scheme utilizes all effective bits of phase accumulator address, and so can improve the performances of DDS, which has-70 dB of spur suppression value. 该方案利用了相位累加器的所有有效位,使DDS的性能得到提高,杂散度抑制比达到了-70dB。
Input data from single-chip produce the frequency word to the implementation of the phase accumulator in FPGA to be on frequency synthesis. Then, use the address data to search wave data exist in RAM already, implementation of the sampling waveform synthesis. 输入频率控制字经由单片机送到FPGA中的相位累加器实现对所要频率的合成,用生成的地址数据查找存在RAM中的相应单个周期波形数据,实现波形的采样合成。